1. Field of the Invention
The present invention relates to non-volatile semiconductor memories. More specifically, the present invention relates to compensating for temperature variations that may occur during operation of the semiconductor memories.
2. Description of Related Art
Non-volatile semiconductor memories are becoming increasingly popular in a wide range of electronic applications from computer systems to personal appliances such as cellular phones, personal digital assistants, cameras, and music players. With the increased popularity, comes increased need for placing larger volumes of data on an individual device and operating the devices with lower power consumption.
Non-volatile memories cells, such as Electrically Erasable Programmable Memories (EEPROMs) and Flash EEPROMs, store information in a field effect transistor (FET) using a floating gate disposed between the substrate and a control gate. FIG. 1 illustrates a flash cell comprising a conventional transistor used in Flash memories. The flash cell 10 includes a drain 12, a source 14, the floating gate 16, and the control gate 18. The floating gate 16 is isolated from the control gate 18 and substrate by dielectric layers formed above and below the floating gate 16. In flash memories, the control gates of a plurality of flash cells are coupled to a word-line. Thus, the signal on the control gate is referred to herein as Vwl, or variations thereof.
Assuming the flash cell is initially erased, the flash cell is programmed by placing charge on the floating gate. Once the charge is stored on the floating gate, it is effectively trapped on the floating gate and remains there even when power is removed. Subsequently, an erase process may be used to remove the stored charge from the floating gate. Programming and erasing are accomplished using a variety of mechanisms well known in the art, such as, avalanche injection, channel injection, and tunneling depending on the structure of the flash cells.
FIG. 2 illustrates current characteristics of a flash cell as a current versus voltage curve. In operation, an erased flash cell exhibits current characteristics as shown by curve 20, which is defined as a binary “1.” When the flash cell is programmed, the additional charge on the floating gate moves the current curve for the flash cell to a higher voltage. The more charge stored on the floating gate, the farther to the right the current curve will move. Curve 30 illustrates the current characteristics of a flash cell safely programmed as a binary “0.” Curve 25 illustrates the current characteristics of a flash cell that is at a minimum acceptable programming to be considered a “0.” Line 40 indicates a current threshold (Ith) at which a sense amplifier distinguishes between a programmed and an unprogrammed flash cell. If a current from the flash cell (Icell) is below Ith, the flash cell will be considered programmed, if Icell is above Ith, the flash cell will be considered unprogrammed. In other words, there is a threshold voltage (Vth), represented by line 50, at which the flash cell conducts a high enough current for the sense amplifier to detect. Thus, after programming, a flash cell may be read by applying a voltage that is midway between an unprogrammed voltage and a programmed voltage. With this voltage applied, if a current is sensed, the flash cell is considered unprogrammed (i.e., “1” in this case). If a current is not sensed, the flash cell is considered programmed (i.e., “0” in this case).
FIG. 3 illustrates the margin that may be present in a flash cell that is programmed relative to a voltage used on the word-line during a read process. Curve 25 illustrates the current characteristics of a flash cell that is at a minimum acceptable programming to be considered programmed. After a flash cell is programmed, a verify process may be done. In the verify process, the flash cell is read using a verify word-line voltage (Vwl_v) that is at the highest voltage acceptable to read out a programmed flash cell to give a current Icell below the threshold current Ith. If a flash cell is not detected as programmed after this verify process, the cell may be programmed again, or it may be marked as a bad cell and replaced with a spare cell. In other words, Vwl_v indicates the highest voltage possible on the word-line to read a cell as unprogrammed. Thus, when the flash cell is read during a normal read operation word-line voltage (Vwl_r) less than Vwl_v is used to ensure that there is margin for distinguishing between a programmed and an unprogrammed flash cell. This margin is illustrated as a “verify margin.”
As stated earlier, the current characteristics of a flash cell may change with changes in temperature. FIG. 4 illustrates this change. Curve 25L illustrates a flash cell programmed at a low temperature. Line Vwl_v(LT) indicates that the flash cell may be verified to be at an acceptable level at the low temperature. However, when the device is at a higher temperature, the flash cell exhibits current curve 25H. At the higher temperature, the highest voltage at which the flash cell may be verified to be programmed is indicated as Vwl_v(HT). Thus, if the read word-line voltage Vwl_r is at the same voltage for both low and high temperatures, a flash cell programmed at a low voltage, but read at a high voltage, has a decreased verify margin, as indicated in FIG. 4. Since the current characteristics of a flash cell may change with changes in temperature, this temperature change may reduce the margin available for distinguishing between a programmed and unprogrammed flash cell.
Furthermore, the location of a cell in a series chain of flash memory cells dictates the threshold voltage of the memory cell. A change in temperature also results in a change in the current flowing through the series chain of memory cells. In FIG. 5, a NAND flash array is comprised of an array of floating gate cells 87 arranged in series cell chains 88, 89. Each of the floating gate cells are coupled drain-to-source in the series cell chains 88, 89. Word-lines (WL_0-WL_15) that span across multiple series cell chains 88, 89 are coupled to the control gates of every floating gate cell in order to control their operation.
In operation, the word-lines (WL_0-WL_15) select the individual floating gate memory cells in the series cell chains 88, 89 to be written to or read from and operate the remaining floating gate memory cells in each series cell chain 88, 89 in a pass through mode. Each series cell chain 88, 89 of floating gate memory cells is coupled to a source line 90 by a source select gate 94, 95 and to an individual bit line (BL1-BLN) by a drain select gate 91, 92. The source select gates 94, 95 are controlled by a source select gate control line SG(S) 96 coupled to the control gates. The drain select gates 91, 92 are controlled by a drain select gate control line SG(D) 93.
It can be seen from FIG. 5 that in order to read one memory cell, current must flow through the other memory cells in the series cell chain 88, 89. Therefore, the remaining cells become parasitic resistances in series with either the drain or source connections. Since the cell_0 98 at the bottom of the series cell chain 88 is closest to the array ground, it sees 15 voltage drops in the drain line and one in the source line. The cell_15 97 at the top of the series cell chain 88 sees 15 voltage drops in the source line and one in the drain line.
It is known that the current of any transistor (i.e., memory cell) is determined by the transistor's Vgs and Vds, depending on the mode of operation. In saturation mode, the current of the cell varies mostly with Vgs and is not a function of Vds. The transistor current varies with the square of Vgs. In linear mode, the current through the cell varies with Vds.
Assuming a particular cell is operating in saturation mode in order to get the highest gain, it can be seen that the cell_0 98 at the bottom of the series cell chain 88 does not experience a voltage drop on its Vgs. The cell_15 97 at the top of the series cell chain 88 sees 15 times the voltage drop in the source voltage. Since the cell current is a function of (Vgs−V1)2, the difference in the source voltages is going to be squared in reflection of the cell current change, Vt (i.e., the threshold voltage) being the same.
The relationship between temperature and threshold voltage or Vt level is a function of the location of a cell in the cell string or chain of memory cells. Accordingly, the variations of the threshold voltage or Vt level is not just a function of the temperature, but is also variable with the location of the cell in the cell string over variations in temperature.
Since the current characteristics of a flash cell may change with changes in temperature, this temperature change may reduce the margin available for distinguishing between a programmed and unprogrammed flash cell. Furthermore, since the threshold voltage or Vt level is also a function of the location of the cell in the string of memory cells, there is a need for generating a word-line voltage to increase margin by modifying the word-line voltage depending on temperature, the properties of a flash cell and the location of the flash cell in the string of cells.